This is an experimental branch that moves the data and instruction memory outside the core, to be replaced with AMBA AXI4/AXI4-Lite bus interfaces. The new core is core-extmem and this modified core does not yet work with the top module.

The changes made to the instmem and datamem modules break top.v and core.v. Do not use this branch if you're trying to use them.

Pipelined RV32IMC Core

This is a RISC-V RV32IMC core that is currently being adapted for implementation in a test chip as part of Center for Integrated Devices Research (CIDR) Project 3.

The top module has been tested on the following FPGAs:

• Artix A7-35T on the Digilent Arty-A7 board (discontinued)
• Artix A7-200T on the Nexys Video Board. Constraints files for both FPGAs are provided as part of the code. Other Artix A7-series FPGAs should work once their respective constraints files are set up.

If you would like to use this core as a reference for your own projects, feel free to cite to cite the paper for the original project.

@INPROCEEDINGS{9293798,
  author={Neri, Michael Joseph and Immanuel Ridao, Redentor and Baylosis, Victor Emmanuel and Meira Chua, Phoebe and Tan, Allen Jason and Theresa de Leon, Maria and Hizon, John Richard and Rosales, Marc and Rouelli Sabino-Santos, Maria Patricia and Santos, Christopher and Alvarez, Anastacia},
  booktitle={2020 IEEE REGION 10 CONFERENCE (TENCON)}, 
  title={Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks}, 
  year={2020},
  volume={},
  number={},
  pages={806-811},
  keywords={Clocks;Registers;Wireless sensor networks;Protocols;Field programmable gate arrays;Process control;Pipelines;RISC-V;Wireless Sensor Networks;Internet of Things;FPGA;Pipelining},
  doi={10.1109/TENCON50793.2020.9293798}}

Pipelined RV32IMC: Capstone Project for CoE 198 (2SAY1920)

This project uses Xilinx IP modules available in Vivado. The design was verified using Vivado 2019.2

Project Members

• Emman Baylosis
• Phoebe Chua
• MJ Neri
• Red Ridao
• Allen Tan

Processor Specifications and Features

Simplified Processor Block Diagram

Data Memory Organization

Creating Vivado Project

• Clone this GitHub repository to your PC
• Add board-files/arty-a7-35 to your Vivado Installation Directory. README.txt contains specific directory.
• Create a project in Vivado. In Boards, select Arty A7-35 (part: xc7a35ticsg324-1L).
• Run project_run.tcl to add all source files to the project (see section below).
• Check for any missing sources. You can double check w/ img/design-hier.png
• To generate dump files for assembly-tests, use dumpgen_script.py

Using project_run.tcl

• Edit SRCDIR in project_run.tcl to location of this repository in your PC
• Execute using Tools > Run Tcl Script... in Vivado
• ...or by invoking source <path to>/project_run.tcl in the Vivado TCL Console.

Using assembler.py

> python assembler\assembler.py <input_file.s> <output_file.dmp> -comp_buffer True

Using dumpgen_script.py

• Set terminal to directory of assembly code before running dumpgen_script.py
• Edit assembler_folder_path in dumpgen_script.py using absolute path
• RARS is used to generate datamem dumps & answer keys

> python dumpgen_script.py <input_file.s>

Using Vivado ILA

• Comment/uncomment ila_ctr in top.v
• Comment/uncomment Vivado ILA section in the constraints file