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Commit 25fecf9a authored by Allen Jason Tan's avatar Allen Jason Tan
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Fix repeated stores + testbench fixes

parent d7b000ec
ext-memory
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with 72 additions and 27 deletions
+72 -27
processor/core-extmem.v
View file @ 25fecf9a
......@@ -37,7 +37,12 @@ module core_extmem (
`else
output [3:0] ext_data_write,
`endif
output [`BUS_BITS-1:0] ext_data_addr,
`ifdef FEATURE_DMEM_BYTE_ADDRESS
output [`BUS_BITS-1:0] ext_data_addr,
`else
output [`DATAMEM_BITS-1:0] ext_data_addr,
`endif
output ext_data_wr_en,
output [`DATAMEM_WIDTH-1:0] ext_data_store,
input [`DATAMEM_WIDTH-1:0] ext_data_load,
......
processor/datamem_interface.v
View file @ 25fecf9a
......@@ -10,7 +10,12 @@ module datamem_interface(
// Pass-through to Datamem
input [`DATAMEM_BITS-1:0] exe_addr_in,
input [`DATAMEM_BITS-1:0] mem_addr_in,
output [`BUS_BITS-1:0] addr_out,
`ifdef FEATURE_DMEM_BYTE_ADDRESS
output [`BUS_BITS-1:0] addr_out,
`else
output [`DATAMEM_BITS-1:0] addr_out,
`endif
// Store Block I/O
input [31:0] sb_opB,
input [1:0] sb_byte_offset,
......@@ -36,7 +41,6 @@ module datamem_interface(
// Core Control I/O
input [`REGFILE_BITS-1:0] mem_rd,
input stall,
output store_sel,
output read_ready
);
......@@ -44,7 +48,11 @@ module datamem_interface(
wire [31:0] lb_data_t;
wire [31:0] sb_data_t;
wire [`DATAMEM_BITS-1:0] addr_out_t;
assign addr_out = {addr_out_t, 2'b0};
`ifdef FEATURE_DMEM_BYTE_ADDRESS
assign addr_out = {addr_out_t, 2'b0};
`else
assign addr_out = addr_out_t;
`endif
`ifdef FEATURE_BIT_ENABLE
wire [31:0] sb_dm_write_t;
`else
......@@ -52,7 +60,7 @@ module datamem_interface(
`endif
wire is_load = (sel_data == 3'd3) && (mem_rd != 0);
wire is_mem_op = sb_is_stype || is_load;
wire is_mem_op = (sb_is_stype || is_load) && ~mem_flush;
wire [`DATAMEM_BITS-1:0] addr_in = (is_load || store_sel) ? mem_addr_in : exe_addr_in;
/*
reg hold;
......
processor/mem_protocol_driver.sv
View file @ 25fecf9a
......@@ -221,7 +221,12 @@ module mem_protocol_driver (
end
end
MEM_WAIT_STORE: begin
ready <= 0;
if (gnt) begin
ready <= 1;
end
else begin
ready <= 0;
end
end
default:
ready <= 0;
......
processor/sf_controller.v
View file @ 25fecf9a
......@@ -260,7 +260,7 @@ module sf_controller(
assign if_flush = ISR_PC_flush;
assign id_flush = (ISR_pipe_flush || jump_flush || branch_flush) || !if_ready;
assign exe_flush = exe_jalr_hazard || branch_flush || (is_nop && ~mem_stall);
assign mem_flush = (div_running || mul_stall) || (load_hazard && dmem_ready);
assign mem_flush = (div_running || mul_stall) || (load_hazard && dmem_ready) || ((exe_opcode == `OPC_STYPE) && dmem_ready);
assign wb_flush = mem_stall;
// Enables
......
sim/tb_core_extmem.sv
View file @ 25fecf9a
......@@ -202,12 +202,14 @@ module tb_core_extmem();
assign dmem_data_write = core_data_write;
`endif
wire [`BUS_BITS-1:0] core_data_addr;
wire [`DATAMEM_BITS-1:0] core_data_addr;
wire [`BUS_BITS-1:0] bus_data_addr = {core_data_addr, 2'b0};
wire [`DATAMEM_WIDTH-1:0] core_data_store;
wire [`DATAMEM_WIDTH-1:0] core_data_load;
wire core_data_request;
wire core_data_grant;
wire core_data_valid;
wire active_data_op = core_data_request || core_data_valid || core_data_grant;
wire [`PC_ADDR_BITS-1:0] core_inst_addr;
wire [`WORD_WIDTH-1:0] core_inst_data;
......@@ -219,7 +221,11 @@ module tb_core_extmem();
.nrst(nrst),
.dm_write(dmem_data_write),
.data_addr(core_data_addr),
`ifdef FEATURE_DMEM_BYTE_ADDRESS
.data_addr(core_data_addr)
`else
.data_addr(bus_data_addr),
`endif
.data_in(core_data_store),
.data_req(core_data_request),
.data_gnt(core_data_grant),
......@@ -257,14 +263,14 @@ module tb_core_extmem();
.ext_data_req(core_data_request),
.ext_data_gnt(core_data_grant),
.ext_data_valid(core_data_valid),
.ext_inst_addr(core_inst_addr),
.ext_inst_data(core_inst_data),
`ifdef FEATURE_INST_TRACE_ENABLE
.ext_if_inst(core_if_inst)
.ext_id_inst(core_id_inst)
.ext_if_inst(core_if_inst),
.ext_id_inst(core_id_inst),
`endif
.ext_inst_addr(core_inst_addr),
.ext_inst_data(core_inst_data)
);
answerkey_i #() AK();
......@@ -301,7 +307,7 @@ module tb_core_extmem();
last_inst = 0;
con_write = 0;
con_addr = 10'h0;
max_data_addr = 0;
max_data_addr = 248;
con_in = 0;
done = 0;
check = 0;
......@@ -322,6 +328,7 @@ module tb_core_extmem();
// The following code is for checking the contents
// of BLOCKMEM
/*
always@(posedge CLK) begin
if(!nrst)
max_data_addr <= 0;
......@@ -336,6 +343,7 @@ module tb_core_extmem();
end
end
end
*/
always@(posedge done) begin
......@@ -381,7 +389,12 @@ module tb_core_extmem();
end
else begin
if (!done) begin
if ((last_inst[15:0] == 16'h0001 || last_inst== 32'h13) && (INST[15:0] == 16'h0001 || INST== 32'h13)) begin
if (active_data_op) begin
last_inst <= INST;
consecutive_nops = 0;
check = 0;
end
else if ((last_inst[15:0] == 16'h0001 || last_inst== 32'h13) && (INST[15:0] == 16'h0001 || INST== 32'h13)) begin
consecutive_nops = consecutive_nops + 1;
check = check + 1;
end
......
sim/tb_core_extmem_single.sv
View file @ 25fecf9a
......@@ -20,10 +20,10 @@ module tb_core_extmem_single();
reg [`WORD_WIDTH-1:0] last_inst;
// localparam string temp_inst = $sformatf("%s%s%s", `REPO_LOCATION, `TEST_LOCATION, "instmem-dump/mem/program_inst.hex");
localparam string temp_inst = $sformatf("%s%s%s", `REPO_LOCATION, `TEST_LOCATION, "instmem-dump/mem/I-SB-01.mem");
localparam string temp_inst = $sformatf("%s%s%s", `REPO_LOCATION, `TEST_LOCATION, "instmem-dump/mem/I-ADD-01.mem");
// localparam string temp_data = $sformatf("%s%s%s", `REPO_LOCATION, `TEST_LOCATION, "datamem-dump/mem/program_data.hex");
localparam string temp_data = $sformatf("%s%s%s", `REPO_LOCATION, `TEST_LOCATION, "datamem-dump/mem/I-SB-01.mem");
localparam string temp_refm = $sformatf("%s%s%s", `REPO_LOCATION, `TEST_LOCATION, "answer-keys/mem/I-SB-01.mem");
localparam string temp_data = $sformatf("%s%s%s", `REPO_LOCATION, `TEST_LOCATION, "datamem-dump/mem/I-ADD-01.mem");
localparam string temp_refm = $sformatf("%s%s%s", `REPO_LOCATION, `TEST_LOCATION, "answer-keys/mem/I-ADD-01.mem");
wire [3:0] dmem_data_write;
`ifdef FEATURE_BIT_ENABLE
......@@ -35,7 +35,7 @@ module tb_core_extmem_single();
`endif
wire [`DATAMEM_BITS-1:0] core_data_addr;
wire [`BUS_BITS-1:0] bus_data_addr = {2'b0, core_data_addr};
wire [`BUS_BITS-1:0] bus_data_addr = {core_data_addr, 2'b0};
wire [`DATAMEM_WIDTH-1:0] core_data_store;
wire [`DATAMEM_WIDTH-1:0] core_data_load;
wire core_data_request;
......@@ -54,6 +54,7 @@ module tb_core_extmem_single();
wire core_data_request;
wire core_data_grant;
wire core_data_valid;
wire active_data_op = core_data_request || core_data_valid || core_data_grant;
wire [`PC_ADDR_BITS-1:0] core_inst_addr;
wire [`WORD_WIDTH-1:0] core_inst_data;
......@@ -65,7 +66,12 @@ module tb_core_extmem_single();
.nrst(nrst),
.dm_write(dmem_data_write),
.data_addr(core_data_addr),
`ifdef FEATURE_DMEM_BYTE_ADDRESS
.data_addr(core_data_addr)
`else
.data_addr(bus_data_addr),
`endif
.data_in(core_data_store),
.data_req(core_data_request),
.data_gnt(core_data_grant),
......@@ -97,20 +103,21 @@ module tb_core_extmem_single();
`endif
.ext_data_write(core_data_write),
.ext_data_addr(core_data_addr),
.ext_data_store(core_data_store),
.ext_data_load(core_data_load),
.ext_data_req(core_data_request),
.ext_data_gnt(core_data_grant),
.ext_data_valid(core_data_valid),
.ext_inst_addr(core_inst_addr),
.ext_inst_data(core_inst_data),
`ifdef FEATURE_INST_TRACE_ENABLE
.ext_if_inst(core_if_inst)
.ext_id_inst(core_id_inst)
.ext_if_inst(core_if_inst),
.ext_id_inst(core_id_inst),
`endif
.ext_inst_addr(core_inst_addr),
.ext_inst_data(core_inst_data)
);
wire [31:0] box;
......@@ -225,7 +232,13 @@ module tb_core_extmem_single();
consecutive_nops = 0;
last_inst = 0;
end
else
else begin
if (active_data_op) begin
last_inst <= INST;
consecutive_nops = 0;
check = 0;
end
else
if (!done)
if ((last_inst[15:0] == 16'h0001 || last_inst == 32'h13) && (INST[15:0] == 16'h0001 || INST == 32'h13)) begin
consecutive_nops = consecutive_nops + 1;
......@@ -239,6 +252,7 @@ module tb_core_extmem_single();
consecutive_nops = 0;
check = 0;
end
end
end
// This controls the NOP counter
always@(posedge CLK) begin
......
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